High-performance computation is the demand of upgrading technology, processing biomedical signals requires the use of numerous signal processing algorithms executing as per described end application. Filtering is a simple but essential operation in most signal-processing algorithms. To maintain signal quality, the ECG signal undergoes various stages of filtering as the ECG signals consist of multiple frequency components and noise. Implementation of the FIR filter is a challenging task for time-critical applications. Parallel FIR filter architectures meet the demand of high computational demand as described for time-critical applications but parallel FIR filters consume a large area and resources to be realized. The presented work gives a performance analysis of a conventional parallel FIR filter with proposed parallel FIR filter architecture on a reconfigurable platform. Improvement in resource utilization is to be noted as the number of DSP48E1s slices consumed in the proposed work is constant with a change in the level of parallelism from 2, 4, 8, and 16 for the FIR filter of order 16. The study depicts the architectural impact of the proposed work and from the comparative analysis, it is observed that the proposed FIR filter architecture uses fewer resources and improves the path delay by 64% while the DSPslices utilization is brought down up to 96%. The presented work is carried out on xc7vx690t-2Lffg1930 Virtex 7 series FPGA with low power grade and tools such as Xilinx ISE14.7, PlanAhead 14.7 are utilized for the design and analysis of the presented work on parallel FIR filter developed for pre-processing of ECG signals.

Bio-medical Signal Processing, Denoising ECG signals, FIR Filter Architectures, Parallel Filter Architectures, FIR on Reconfigurable Architecture, High-speed FIR Filter, FPGA.