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Edited by: Editorial Board of Journal of Data Acquisition and Processing
P.O. Box 2704, Beijing 100190, P.R. China
Sponsored by: Institute of Computing Technology, CAS & China Computer Federation
Undertaken by: Institute of Computing Technology, CAS
Published by: SCIENCE PRESS, BEIJING, CHINA
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      09 May 2023, Volume 38 Issue 3
    Article

    DESIGN AND IMPLEMENTATION OF D FLIP-FLOP FOR AREA EFFICIENT, LOW POWER APPLICATIONS USING MGDI TECHNIQUE
    Renita Pearlin T, Dr. Bhavani S, Madhuvarshini M, Roshini S N
    Journal of Data Acquisition and Processing, 2023, 38 (3): 257-267 . 

    Abstract

    After the emerge of VLSI in this world, it had made the innovation to grow at faster rate. VLSI chiefly centres around lessening the number of transistors, area, power and delay which are the major standards of it. These factors improve the VLSI products to be cost effective, highly reliable, improved performance and increases the operating speed with less power. USR has various applications like memory blocks in PC’s, serial and parallel data transfer and data converters, micro-controllers etc. In this paper, the idea of reduced area, low power and less delay is presented with m-GDI technique. This paper is based on designing the front-end and back-end of 8-bit USR using m-GDI technique in cadence virtuoso tool utilizing gpdk45 library. The examination table of area, power and delay using m-GDI, GDI and CMOS technique is also illustrated.

    Keyword

    Modified Gate Diffusion Input, 8-bit USR, area, power, delay, transistor, layout, cadence, virtuoso tool, gpdk45 library, CMOS technology.


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ISSN 1004-9037

         

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